The present invention relates to a manufacturing method of a semiconductor device and can be preferably applied, for example, to a manufacturing method of a semiconductor device which uses, when forming field effect transistors with different power supply voltages over a semiconductor substrate, a gate-last process of forming a gate electrode after having performed heat treatment to activate the semiconductor region for the source and drain.
A semiconductor device such as an MCU (Micro Controller Unit) or an SoC (System on Chip) has a high-voltage MOSFET (Metal Oxide Semiconductor Field Effect Transistor) driven by a high power supply voltage and a core MOSFET driven by a low power supply voltage formed over a semiconductor substrate.
The gate length of a core MOSFET is being reduced every year for a higher performance, a higher functionality and a higher integration, and for an advanced product using a planar core MOSFET, the gate length has attained 20 to 40 nm. In addition, the most advanced product with a three-dimensional gate structure has attained a gate length shorter than 20 nm.
On the other hand, there is a demand for a high-voltage MOSFET that, in order to ensure the reliability for the hot carrier and the breakdown voltage between the source and drain thereof and the semiconductor substrate, the source and drain thereof should be formed deeper with a gradual impurity distribution compared to the source and drain of a core MOSFET. When forming a MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type flash memory over a semiconductor substrate, for example, a power supply voltage of 5 V is often required for the high-voltage MOSFET, for which ensuring the reliability and the breakdown voltage of the high-voltage MOSFET has become an important issue.
Descriptions of a method of forming field effect transistors with different power supply voltages over a same semiconductor substrate are provided in Patent Document 1 (Japanese Patent Laid-Open No. 2006-245167), Patent Document 2 (Japanese Patent Laid-Open No. 2000-243937) and Patent Document 3 (Japanese Patent Laid-Open No. 2007-305711), for example, each of which discloses a manufacturing method of a semiconductor device using a gate-first process of performing heat treatment to activate the semiconductor region for the source and drain after forming the gate electrode.
In addition, there is disclosed in Patent Document 4 (Japanese Patent Laid-Open No. 2007-150321), for example, a manufacturing method of a semiconductor device using a gate-last process of forming a gate electrode after performing heat treatment to activate the semiconductor region for the source and drain.